Integrated circuits for ultra-low power applications strive to minimize total system energy while satisfying performance requirements. The supply voltage (Vdd) can be set to a Minimum Energy Point (MEP), where leakage and dynamic energy are suitably balanced. However, controlling operating frequency (fclk) while concurrently tracking a MEP sensitive to PVT and switching activity is not possible. Meanwhile, the traditional approach of locking to the minimum required frequency (ftarg), and adjusting Vdd to maintain timing slack precludes the possibility of minimum energy computing. Therefore, there exists a need for a minimum energy computing architecture that meets performance requirements.
Prior work has demonstrated MEP tracking across PVT and switching activity variation. The approach relies on large capacitors for sample-and-hold operation at subthreshold frequencies, and cannot account for the significant regulator losses (often amounting to 10%–50% of total energy) necessary for total system energy minimization. Furthermore, clock generation using a free-running oscillator is a requirement in prior work, precluding any regulation of fclk.
This effort explores a digital architecture for total system energy minimization subject to perfor-mance requirements (see Figure). The design supports two modes of operation — MEP-lock and perf-lock — and seamless, uninterrupted execution during transitions between them. In MEP-lock¬, the design tunes Vdd to first search for and then track the minimum total Energy Per Cycle (tEPC) point inclusive of regulator losses.
More details can be found in our upcoming ISSCC Paper.