Clock power remains a substantial contributor to power dissipation, from ultra-low power to high-performance systems. Recently, resonant clocking has been shown to achieve power reduction in clock distribution networks. However, the limited voltage-frequency (VF) scalability of resonant clocking implementations remains a key drawback. Continued aggressive use of DVFS will require efficient resonant clocking across the increasingly wider operating range of the system. In this paper, we present a test-chip implementing Quasi-Resonant Clocking (QRC), the first-ever voltage-scalable, frequency-independent and DVFS enabled resonant clock architecture. The test-chip achieves a 32%-47% clock power reduction over a 0.7V-1.2V supply-voltage range.
More details can be found in our ISSCC paper.