The increase in the volume of private data communication between networked devices has created a demand for true random number generators (TRNGs) which are key building blocks in a variety of digital cryptographic systems. Hardware TRNG implementations typically exploit device noise as an entropy source for random bit generation [2]. TRNGs based on timing jitter are simpler to implement in scaled technologies but are dissipative and achieve lower performance compared to metastability-based TRNGs [4]. However, metastability-based TRNGs typically require careful design and calibration to mitigate the impact of PVT variation. Moreover, both jitter and metastability-based TRNGs in standard CMOS exhibit weak randomness due to correlation arising from substrate coupling and 1/f noise, affecting both the quality and output rate of generated bits.
This project presents an energy-efficient versatile, NIST-compliant TRNG architecture capable of generating random bits from an imperfect physical random-number-generator (PRNG) with significant levels of bias and correlation. The key idea behind the proposed architecture is to exploit efficient hardware implementations of 1) a Markov chain-based de-correlator that removes the autocorrelation of an incoming PRNG bit-stream, and 2) a 4-level, Iterative Von-Neumann (IVN) corrector that removes bias from de-correlated bits. The ASIC implementation of the TRNG, combined with a PRNG based on sense amplifier meta-stability, achieves a peak energy efficiency of 2.58 pJ/bit while operating over a wide voltage and frequency range of 0.5–1 V and 4.4–200 MHz respectively.
More details will be posted upon publication of this work.