PSyLab

Digital, Mixed-signal and Integrated Power Circuits and Architectures

Sarah Miller

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Diego Pena

Diego is a Ph.D. student in the Processing Systems Laboratory of the Electrical and Computer Engineering at the Georgia Institute of Technology. He received M.Sc. degrees in Applied Mathematics and Electrical Engineering, both from University of Washington (Seattle, WA) in 2022, and his B.Eng. degree in Electronics Engineering from Universidad Simón Bolívar (Caracas, Venezuela) in 2018. During the summer of 2022 Diego was an intern with Apple Inc. in Sunnyvale, CA, and during the summer of 2016 he was a summer student at CERN, in Geneva, Switzerland. His research focuses on Digital VLSI and Computer Architecture, especially on applying mathematical optimization ideas to hardware design problems, and on efficient hardware implementations of runtime control and signal processing algorithms.

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Energy-efficient, Robust True Random Number Generators (TRNGs)

(Top) Flicker noise and finite circuit bandwidth result in filtered noise used for random bit generation, leading to correlation between successive random bits. (Bottom) Correlation and bias from an imperfect physical RNG are removed in two all-digital post-processing stages

The increase in the volume of private data communication between networked devices has created a demand for true random number generators (TRNGs) which are key building blocks in a variety of digital cryptographic systems. Hardware TRNG implementations typically exploit device noise as an entropy source for random bit generation [2]. TRNGs based on timing jitter are simpler to implement in scaled technologies but are dissipative and achieve lower performance compared to metastability-based TRNGs [4]. However, metastability-based TRNGs typically require careful design and calibration to mitigate the impact of PVT variation. Moreover, both jitter and metastability-based TRNGs in standard CMOS exhibit weak randomness due to correlation arising from substrate coupling and 1/f noise, affecting both the quality and output rate of generated bits.

This project presents an energy-efficient versatile, NIST-compliant TRNG architecture capable of generating random bits from an imperfect physical random-number-generator (PRNG) with significant levels of bias and correlation. The key idea behind the proposed architecture is to exploit efficient hardware implementations of 1) a Markov chain-based de-correlator that removes the autocorrelation of an incoming PRNG bit-stream, and 2) a 4-level, Iterative Von-Neumann (IVN) corrector that removes bias from de-correlated bits. The ASIC implementation of the TRNG, combined with a PRNG based on sense amplifier meta-stability, achieves a peak energy efficiency of 2.58 pJ/bit while operating over a wide voltage and frequency range of 0.5–1 V and 4.4–200 MHz respectively.

More details will be posted upon publication of this work.

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MATIC

As a result of the increasing demand for deep neural network (DNN)-based services, efforts to develop dedicated hardware accelerators for DNNs are growing rapidly. However, while accelerators that have high performance and efficiency on convolutional deep neural networks (Conv-DNNs) have been developed, less progress has been made with regards to fully- connected DNNs (FC-DNNs), which are inherently memory-bound.

In this work, we propose MATIC (Memory Adaptive Training with In-situ Canaries), a methodology that enables aggressive voltage scaling of accelerator weight memories to improve the energy-efficiency of DNN accelerators. To enable accurate operation with voltage overscaling, MATIC combines the characteristics of destructive SRAM reads with the error resilience of neural networks in a memory-adaptive training process. Furthermore, PVT-related voltage margins are eliminated using bit-cells from synaptic weights as in-situ canaries to track runtime environmental variation. Demonstrated on a low-power DNN accelerator fabricated in 65 nm CMOS, MATIC enables up to 60-80 mV of voltage overscaling (3.3× total energy reduction versus the nominal voltage), or 18.6× application error reduction.

Further details about this work can be found in the Date paper and in the expanded TCAS-1 paper

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High-Density Neural Signal Recording

A new neural recording (ECoG) architecture that exploits signal statistics to achieve 14b of conversion range by combining 8-bit Nyquist ADC and DAC modules, and achieves a 10X improvement in recording density over state-of-the-art
A new neural recording (ECoG) architecture that exploits signal statistics to achieve 14b of conversion range by combining 8-bit Nyquist ADC and DAC modules, and achieves a 10X improvement in recording density over state-of-the-art

Chronic brain computer interface (BCI) applications face several key engineering challenges. Future BCIs will require both high electrode density and large spatial coverage, resulting in thousands of electrodes. BCIs require closed-loop neuromodulation, which generates large stimulation artifacts that obfuscate important signals shortly after stimulation. Power density requirements due to tissue heating remain restrictive, particularly in monolithic solutions. Additionally, a single-chip solution with efficient operation for both electrocorticography (ECoG) (<500Hz signals) and single neuron recording (<10kHz signals) is highly desirable.

In this project, we demonstrate a channel, process and frequency scalable, recording system in standard TSMC 65nm CMOS. Key contributions of this architecture to the state-of-the-art are: 10x higher recording channel density by using highly multiplexed recording channels; robust operation that combines low-precision data conversion to achieve high-precision recording; realtime common-mode and differential-mode artifact suppression at the amplifier inputs. The system scales gracefully in frequency and channel-count without significantly affecting efficiency, making it useful for a variety of biopotential acquisition applications.

More details can be found in our VLSI Symposium Paper

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Xun Sun

Xun received the B.S. degrees in Electrical Engineering from University of Michigan, Ann Arbor, MI and from Shanghai Jiao Tong University, Shanghai, China in 2016. Currently, she is pursuing the Ph.D. degree in Electrical Engineering at University of Washington. Her research interests include integrated power converters, low-power mixed signal circuits, and the application of control ideas to power-management problems.

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Evren Basaran

Evren Basaran is a Turkish-American fourth year undergraduate. He is finishing his bachelors in May 2024 and returning for his masters. His research interests include energy-efficient IC design, digital circuits, and clocking. He enjoys hiking, chess and building computers.