PSyLab

Digital, Mixed-signal and Integrated Power Circuits and Architectures

Sarah Miller

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Switched-Capacitor UniCAP

The proliferation of Internet-of-Things (IoT) devices has provided an unprecedented demand for ultra-low power systems, where dissipative Process, Voltage and Temperature (PVT) related supply margins, and low cost, low form-factor power management solutions are key considerations. Switched Capacitor (SC) converters are well-suited to such systems and offer efficient integrated DC-DC conversion. However, poor load regulation results in additional droop guard-bands, amplifying the existing problem of PVT-margin related inefficiencies. Another challenge facing low-voltage (near- and sub-threshold) systems is the need to achieve fine-grained voltage scalability with good load regulation. Several integrated voltage regulation (IVR) solutions have been proposed to address supply and PVT-related margins.

This project sees to develop an all-digital Unified Clock and Power (UniCaP) architecture for performance-regulation of near-Vth and sub-Vth digital systems, and demonstrate its effectiveness on an ARM Cortex-M0 processor with an FFT accelerator. UniCaP is based on the observation supply-voltage control in low-voltage digital systems is tasked with ensuring timing-slack. The central idea behind this UniCaP design is to use canary-based oscillators powered by the noisy load domain (Vdd) to guarantee timing compliance, and incorporate voltage-regulation into a Frequency Locked Loop to control Vdd to regulate system operating frequency (fclk) under PVT variation and supply noise. Key features demonstrated by test measurements include (i) a 92% average reduction in supply-droop margin (ii) 98% reduction of temperature related Vdd margins amounting to XmV (YmV) at 0.45V (0.56V) Vdd in the -20C—100C range (iii) continuous SC Vdd-scalability with excellent load and line regulation (iv) a floating split-level supply rail for robust, efficient SC operation independent of Vdd conversion and (v) simplified, on-the-fly DVFS avoiding use of Voltage-frequency tables and enabling uninterrupted processor operation.

Preliminary results on our research in this area were presented at ISSCC 2018.

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Buck Converter UniCAP

Unified Clock and Power (UniCaP) combines the traditionally disparate clock and power sub-systems into a single control structure to enable unprecedented regulation capabilities, and the ability to virtually eliminate droop and temperature related supply-margins

Integrated Voltage Regulation (IVR) using buck converters enables efficient, fine-grained supply-voltage control in modern SoC domains. However, existing IVR implementations face several challenges. As voltage domains continue to shrink, reduced per-domain decoupling capacitance requires rapid IVR transient response, leading to unfavorable efficiency and supply droop margin trade-offs. Additionally, digital domains exhibit a wide load current (Iload) range, requiring capabilities for autonomous transition between Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). All-digital IVR solutions are particularly desirable for ease of integration in SoCs.

Several techniques have been proposed to address these IVR challenges, including adaptive clocking techniques that maintain timing-slack by injecting load-domain supply (Vdd) noise into Phase-locked Loops (PLLs) to modulate the clock period (Tclk). However, benefits observed using these techniques are limited by Vdd-delay sensitivity mismatch between critical paths and the PLL oscillator, and by the undesirable phase tracking mechanism of conventional PLLs. Importantly, existing adaptive clocking techniques are unable to completely restore cycles lost or gained during Vdd transients, a highly desirable feature for inter-domain data communication and real-time applications.

This project has resulted in a unified clock and power (UniCaP) architecture that exploits joint supply-voltage and phase/frequency control to aggressively reduce dissipative Vdd margins arising from supply-noise and temperature variation. In addition, UniCaP enables complete recovery of any cycles gained or lost during supply noise events.

Preliminary results on our research in this area were presented at ISSCC 2018.

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Quasi-Resonant Clocking

Quasi-Resonant Clocking (QRC) exploits run-time control to generate trapezoidal-shaped resonant clocks

Clock power remains a substantial contributor to power dissipation, from ultra-low power to high-performance systems. Recently, resonant clocking has been shown to achieve power reduction in clock distribution networks. However, the limited voltage-frequency (VF) scalability of resonant clocking implementations remains a key drawback. Continued aggressive use of DVFS will require efficient resonant clocking across the increasingly wider operating range of the system. In this paper, we present a test-chip implementing Quasi-Resonant Clocking (QRC), the first-ever voltage-scalable, frequency-independent and DVFS enabled resonant clock architecture. The test-chip achieves a 32%-47% clock power reduction over a 0.7V-1.2V supply-voltage range.

More details can be found in our ISSCC paper.

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Graduate Student Research Assistant (Ph.D)

1 Position

PSyLab currently has one funded position in the group for the academic year 2022-2023 in the area of energy-efficient IC design (clocking, voltage-regulation, processor design) or baseband processor design employing run-time inference.

The group welcomes enthusiastic, curious students who are committed to conducting research with the highest standards of quality and integrity. A strong foundation in basic Electrical and Computer Engineering concepts, and an interest in integrated system design (Digital/Analog/Mixed-signal) is essential. An interest in control systems, signal processing, computer architecture, or communication electronics is a plus. However, we are primarily interested in critical thinkers with solid foundations, a good work-ethic and an eagerness to learn. We’ll work out the rest in the fullness of time.

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Graduate Student Research Assistant (MS)

2 Positions

We typically invite 1-2 promising students each year to join the group and take part in research and professional development activities. Funding is NOT guaranteed, and depends on a variety of considerations including the research project and opporutnities for Teaching Assistants. For unfunded positions, student exposure and training are accorded a much higher priority over specific research goals.

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Undergraduate Researcher

2 Positions

The group welcomes enthusiastic, motivated undergraduates from EE/CE/Math/Physics, with a strong grounding in at least one area of integrated system development (e.g., digital/analog design, power systems, computer architecture, IC testing). Students will either take on a directed project to build system modules to be used in research applications, develop test infrastructure (e.g., test PCB’s, FPGA emulators), or team up with graduate students to assist and collaborate on solving challenging research problems in the areas of signal processing control, optimization and data-driven regression.