Chronic brain computer interface (BCI) applications face several key engineering challenges. Future BCIs will require both high electrode density and large spatial coverage, resulting in thousands of electrodes. BCIs require closed-loop neuromodulation, which generates large stimulation artifacts that obfuscate important signals shortly after stimulation. Power density requirements due to tissue heating remain restrictive, particularly in monolithic solutions. Additionally, a single-chip solution with efficient operation for both electrocorticography (ECoG) (<500Hz signals) and single neuron recording (<10kHz signals) is highly desirable.
In this project, we demonstrate a channel, process and frequency scalable, recording system in standard TSMC 65nm CMOS. Key contributions of this architecture to the state-of-the-art are: 10x higher recording channel density by using highly multiplexed recording channels; robust operation that combines low-precision data conversion to achieve high-precision recording; realtime common-mode and differential-mode artifact suppression at the amplifier inputs. The system scales gracefully in frequency and channel-count without significantly affecting efficiency, making it useful for a variety of biopotential acquisition applications.
More details can be found in our VLSI Symposium Paper