Publications

2025

April

A 32-channel 85.4dB SNDR Time-multiplexed Neural Recording Front-end Achieving within-conversion Artifact Recovery ,

A. Mandal, C. Huang, J. Arenas, W. Lee, P. Anschutz, A. Jacob, K. Ramachandra, S. Sober, M. Bakir, S. Li and V. S. Sathe, to appear in Custom Integrated Circuits Conference 2025

A 0.14 J per-Acquisition Frequency-Domain GPS Correlator using Adaptive Compressive Sampling,
Jung-Jin Park, and V. S. Sathe, to appear in, Custom Integrated Circuits Conference 2025

FEB

A Dynamically Reconfigurable Digital Integrated Voltage Regulator Fabric for Energy-Efficient DVFS in Multi-domain SoCs,

J. Arenas, H. Ozturk and V. S. Sathe, to appear in International Solid-State Circuits Conference, Jan. 2025.

A Dual Vdd-Temperature Sensor employing Sensor Fusion with 2.4°C, 9mV (6σ) Inaccuracy in 65nm CMOS,

Ozturk, J. Arenas, C. Tokunaga, N. Kurd and V. S. Sathe, to appear in International Solid-State Circuits Conference, Feb. 2025.

2023

JAN

Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains

Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, and Visvesh Sathe

JSSC 2023

2022

SEP

A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver

Deniz Dosluoglu, Kun-Da Chu, Diego Pena-Colaiocco, Ivan Zhao, Visvesh Sathe, Jacques C Rudell

ESSCIRC 2022

MAY

An All-Digital 1Mbps, 57pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65nm CMOS

Energy Minimization of Duty Cycled Domains through Domain Decoupling Capacitance Energy Recycling and Autonomous Energy Tracking

James D Rosenthal, Arindam Mandal, Visvesh Sathe, Matthew S Reynolds

RFID 2022

APR

CANDLES: Channel-aware novel dataflow-microarchiecture co-design for low energy sparse neural network acceleration

Sumanth Gudaparthi, Sarabjeet Singh, Surya Narayanan, Rajeev Balasubramonian, Visvesh Sathe

HPCA 2022

FEB

Energy Minimization of Duty Cycled Domains through Domain Decoupling Capacitance Energy Recycling and Autonomous Energy Tracking

Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, and Visvesh Sathe

ISSCC 2022

An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS

Diego Peña-Colaiocco, Chi-Hsiang Huang, Kun-Da Chu, Jacques C. Rudell, and Visvesh Sathe

ISSCC 2022

JAN

Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control

Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, and Visvesh Sathe

JSSC 2022

2021

APR

A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation

A. Mandal, D. Pena-Colaiocco, V. Pamula, K. Khateeb, L. Murphy, A. Yazdan, S. Perlmutter, F. Pape, J. Rudell, V. Sathe

CICC 2021

FEB

A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS

C-H. Huang, X. Sun, Y. Chen, V. Pamula, A. Mandal, V. Sathe

ISSCC 2021

2020

SEP

A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation

F. Rahman, G. Taylor and V. S. Sathe

JSSC, vol. 54 no. 9, Sep 2019

JUL

A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS
J. Uehlin, W. Smith, V. Pamula, E. Pepin, S. Perlmutter, V. Sathe, J. Rudell
JSSC, vol. 55, no. 7, Jul. 2020

JUN

Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS

X. Sun, A. Boora, V. Pamula, C-H. Huang, D. Pena-Colaiocco and V. S. Sathe

VLSI Symposium 2020

2019

SEP

A 10b 120MS/s SAR ADC with Reference RippleCancellation Technique

X. Tang, Y. Shen, L. Shen, W. Zhao, Z. Zhu, V. S. Sathe and N. Sun

CICC 2019

FEB

Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS

F. Rahman, R. Pamula, A. Boora and V. S. Sathe

ISSCC 2019

A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS

X. Sun, A. Boora, W. Zhang, R. Pamula and V. S. Sathe

ISSCC 2019

2018

DEC

Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors

S. Kim, P. Howe, T. Moreau, A. Alaghi, L. Ceze and V. S. Sathe

Transactions on Circuits and Systems-1

NOV

Architecture Considerations for Stochastic Computing Accelerators

V. Lee, A. Alaghi, R. Pamula, V. S. Sathe, L. Ceze and M. Oskin

Transactions on Computer-Aided Design of Integrated Circuits and Systems

JUN

An all-digital true-random-number generator with integrated de-correlation and bias correction at 3.2-to-86 Mb/s, 2.58 pJ/bit in 65-nm CMOS

R. Pamula, X. Sun, S. Kim, F. Rahman F. Rahman and V. S. Sathe

IEEE International Symposium on VLSI Circuits (VLSI-Circuits)

An all-digital unified clock frequency and switched-capacitor voltage regulator for variation tolerance in a sub-threshold ARM Cortex M0 processor

F. Rahman, S. Kim, N. John, R. Kumar, R. Pamula and V. S. Sathe

IEEE International Symposium on VLSI Circuits (VLSI-Circuits)

Quasi-resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking for DVFS Systems

F. Rahman, and V. S. Sathe

Journal of Solid-State Circuits (JSSC)

FEB

MATIC: Learning Around Errors for Efficient Low-Voltage Neural Network Accelerators

S. Kim, P. Howe, T. Moreau, A. Alaghi, L. Ceze, and V. S. Sathe

Design Automation & Test in Europe Conference & Exhibition (DATE)

A Combined All-Digital PLL-Buck Slack Regulation System with Autonomous CCM/DCM Transition Control and 82% Average Voltage-Margin Reduction in a 0.6-to-1.0V Cortex-M0 Processor

X. Sun, S. Kim, F. Rahman, R. Pamula, X. Li, N. John, and V. S. Sathe

IEEE International Solid-State Circuits Conference (ISSCC)

2017

JUN

Computational locking: Accelerating lock-times in all-digital PLLs

F. Rahman, G. F. Taylor and V. S. Sathe

IEEE International Symposium on VLSI Circuits (VLSI-Circuits)

A scalable, highly-multiplexed delta-encoded digital feedback ECoG recording amplifier with common and differential-mode artifact suppression

W. A. Smith, J. P. Uehlin, S. I. Perlmutter, J. C. Rudell and V. S. Sathe

IEEE International Symposium on VLSI Circuits (VLSI-Circuits)

Exploring Computation-Communication Tradeoffs in Camera Systems

A. Mazumdar, T. Moreau, S. Kim, M. Cowan, A. Alaghi, L. Ceze, M. Oskin, and V. Sathe

IEEE International Symposium on Workload Characterization (IISWC)

MAR

Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing

V. T. Lee, A. Alaghi, J. P. Hayes, V. S. Sathe and L. Ceze

Design Automation & Test in Europe Conference & Exhibition (DATE)

FEB

Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 μW Analog Front End with Reduced ADC Resolution Requirements

William A. Smith, Brian J. Mogen, Eberhard E. Fetz, V. S. Sathe, and Brian P. Otis

IEEE Transactions on Biomedical Circuits and Systems (TBioCAS)

2016

SEP

UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction

S. Gangopadhyay, S. B. Nasir, A. Subramanian, V. S. Sathe, and A. Raychowdhury

IEEE European Solid-State Circuits Conference (ESSCIRC)

AUG

Regenerative Breaking: Recovering Stored Energy from Inactive Voltage Domains for Energy-efficient Systems-on-Chip

A. Najafi, J. C. Rudell, and V. S. Sathe

IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)

MAY

A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Applications

C. Huang, Y. Chen, T. Zhang, V. S. Sathe, and J. C. Rudell

IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

FEB

Voltage-Scalable Frequency-Independent Quasi-Resonant Clocking Implementation of a 0.7-to-1.2V DVFS System

F. U. Rahman, and V. S. Sathe

IEEE International Solid-State Circuits Conference (ISSCC)

2015

AUG

Fully-Integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS

X. Mi, D. Mandal, V. S. Sathe, B. Bakkologlu, and J. Seo

IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)

Analysis and optimization of CMOS switched-capacitor converter

V. S. Sathe, and J.Seo

IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)

2014

AUG

Quasi-Resonant Clocking : A Run-time Control Approach for True Voltage-Frequency-Scalability

V. S. Sathe

IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)

A deterministic-dither-based, all-digital system for on-chip power supply noise measurement

K. Sankaragomathi, W. A. Smith and V. S Sathe

IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)

2013

JUN

Inductor Design for Global Resonant Clock Distribution

V. S. Sathe, A. Loke, T. Khan, V. Ross, A. Raman, G. Vandevalk, P. Papadopoulos and N. Provatas

ACM/EDAC/IEEE Design Automation Conference (DAC)

JAN

Resonant Clock Design for a Power-efficient, High-volume x86-64 Microprocessor
V. S. Sathe, S. Arekapudi, A. Ishii, C. Ouyang, M. C. Papaefthymiou, and S. Naffziger
Journal of Solid-State Circuits (JSSC), Special Issue on ISSCC‘12 (invited paper)

2012

FEB

Resonant clock design for a power-efficient, high-volume x86-64 microprocessor

V. S. Sathe, S. Arekapudi, A. Ishii, C. Ouyang, M. Papaefthymiou and S. Naffziger

IEEE International Solid-State Circuits Conference (ISSCC)

2010

APR

187MHz subthreshold-supply charge-recovery FIR

W. S. Ma, J. C. Kao, V. S. Sathe, and M. C. Papaefthymiou

Journal of Solid-State Circuits (JSSC), Special Issue on 2009 Symposium on VLSI Circuits (invited paper)

FEB

A 32nm fully-integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency

H.-P. Le, M. Seeman, S. Sanders, V. S. Sathe, S. Naffziger, and E. Alon

IEEE International Solid-State Circuits Conference (ISSCC)

2009

SEP

A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead

J. C. Kao, W. S. Ma, V. S. Sathe, and M. C. Papaefthymiou

IEEE European Solid-State Circuits Conference (ESSCIRC)

A resonant-clock 200MHz ARM926EJ-S™ microcontroller

M. C. Papaefthymiou, A. Ishii, J. Kao., and V. S. Sathe

IEEE European Solid-State Circuits Conference (ESSCIRC)

JUN

A 187MHz subthreshold-supply robust FIR filter with charge-recovery logic

W. S. Ma, J. C. Kao, V. S. Sathe, and M. C. Papaefthymiou

IEEE International Symposium on VLSI Circuits (VLSI-Circuits)

APR

Resonant-clock latch-based design

V. S. Sathe, J. Kao and M. C. Papaefthymiou

Journal of Solid-State Circuits (JSSC), Special Issue on 2007 Symposium on VLSI Circuits (invited paper)

2007

SEP

A 0.8-1.2GHz single-phase resonant-clocked FIR filter with level-sensitive latches

V. S. Sathe, J. C. Kao, and M. C. Papaefthymiou

IEEE Custom Integrated Circuits Conference (CICC)

JUN

RF2: A 1GHz FIR filter with distributed resonant clock generator

V. S. Sathe, J. C. Kao, and M. C. Papaefthymiou

IEEE International Symposium on VLSI Circuits (VLSI-Circuits)

APR

On-chip synchronous communication between clock domains with quotient frequencies

V. S. Sathe, M. C. Papaefthymiou, S. V. Kosonocky, and S. Kim

Electronics Letters, vol. 43, no. 9, pp. 497–499, Apr. 2007.

JAN

Energy-efficient GHz-class charge-recovery logic

V. S. Sathe, J.-Y. Chueh, and M. C. Papaefthymiou

Journal of Solid-State Circuits (JSSC), Special Issue on ISSCC‘06 (invited paper).

2006

SEP

900MHz to 1.2GHz two-phase resonant clock network with programmable driver and loading

J.-Y. Chueh, V. S. Sathe, and M. C. Papaefthymiou

IEEE Custom Integrated Circuits Conference (CICC)

FEB

A 1.1GHz charge-recovery logic

V. S. Sathe, J-Y. Chueh, and M. C. Papaefthymiou

IEEE International Solid-State Circuits Conference (ISSCC)

2005

AUG

A GHz-class charge-recovery logic

V. S. Sathe, C. H. Ziesler, and M. C. Papaefthymiou

IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)

MAY

Fast, efficient, recovering and irreversible

V. S. Sathe, J-Y. Chueh, J. Kim, C.H. Ziesler, S. Kim, and M. C. Papaefthymiou

Conference on Computing Frontiers, pp. 407–413, Ischia, Italy, 2005.

Two-phase resonant clock distribution

J-Y. Chueh, V. S. Sathe and M. C. Papaefthymiou

IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 65–70, Tampa, FL, 2005.

Boost logic: A high-speed energy-recovery circuit family

V. S. Sathe, C. H. Ziesler and M. C. Papaefthymiou

IEEE International Symposium on VLSI Circuits (VLSI-Circuits)

2004

SEP

A synchronous interface for SoCs with multiple clock domains

V. S. Sathe, S. Kim, S. Kosonocky, and M. C. Papaefthymiou

IEEE International System-on-Chip Conference (SOCC)

2003

AUG

A 225 MHz resonant clocked ASIC

C. H. Ziesler, J. Kim , V. S. Sathe and M. C. Papaefthymiou

IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)