Research Areas
Energy-Efficient Computing : From uW-Sensors to kW-Servers
Thermal Sensing for 3D SoC Technologies
Exploring modular temperature sensor architectures for runtime thermal management in 3DICs.
Computationally Enabled Minimum Energy Point Tracking
A digital technique to determine total energy consumed per computation, inclusive of regulator losses, and dynamically set supply-voltage for minimum energy dissipation subject to minimum performance requirements
Computationally-Controlled LDOs
A (significantly) simplified Model Predictive Control approach to optimizing regulator dynamics
Switched-Capacitor UniCAP
Demonstrating Unified Clock And Power architecture with a low-voltage switched-capacitor integrated voltage regulator.
Buck Converter UniCAP
A unified clock and power regulation architecture for digital SoC domains, virtually eliminating supply noise and temperature-related supply guardbands.
On-Chip Power Supply Measurement
Techniques for measuring on-chip supply noise with millivolt resolution and multi-GHz bandwidth.
Run-time Control and Optimization for Systems-in-Package
Computationally locked PLLs
Reducing PLL lock time for cold-start and relock by an order of magnitude.
Computationally Enabled Minimum Energy Point Tracking
A digital technique to determine total energy consumed per computation, inclusive of regulator losses, and dynamically set supply-voltage for minimum energy dissipation subject to minimum performance requirements
Computationally-Controlled LDOs
A (significantly) simplified Model Predictive Control approach to optimizing regulator dynamics
Next-Generation Clocking Architectures: Synthesis and Distribution
Computationally locked PLLs
Reducing PLL lock time for cold-start and relock by an order of magnitude.
Buck Converter UniCAP
A unified clock and power regulation architecture for digital SoC domains, virtually eliminating supply noise and temperature-related supply guardbands.
Quasi-Resonant Clocking
The first-ever voltage-scalable, frequency-independent and DVFS-enabled resonant clock architecture.
Baseband Processing
Computationally locked PLLs
Reducing PLL lock time for cold-start and relock by an order of magnitude.
Buck Converter UniCAP
A unified clock and power regulation architecture for digital SoC domains, virtually eliminating supply noise and temperature-related supply guardbands.
Quasi-Resonant Clocking
The first-ever voltage-scalable, frequency-independent and DVFS-enabled resonant clock architecture.
Neural Interfaces : Realizing Chronic Low-Latency Neuromodulation
High-Density Neural Signal Recording
A multiplexed neural-recording front-end that exploits neural-signal statistics to achieve a robust architecture with 10X improvement in neural recording density.
Machine Learning: Beyond Accelerators
MATIC
Learning around failures in low-voltage on-chip memories to enable energy-efficient neural network accelerators.
Hardware Security
Energy-efficient, Robust True Random Number Generators (TRNGs)
Digital true random-number generation with imperfect entropy sources.