Arindam received his B.Tech degree from Indian Institute of Technology, Kharagpur in 2015. After that he worked a Junior Research Fellow on the design of DC-DC power converters at the same institute till 2016. He completed his Masters degree in 2018 from the University of Maryland, College Park. He joined PSyLab in Fall 2018 to pursue PhD in Electrical Engineering. His current research interest include analog and mixed-signal circuit design for biomedical applications.
Chi-Hsiang received his B.S. and M.S. degrees in Electrical Engineering from National Cheng Kung University (NCKU), Tainan, Taiwan in 2015 and 2017, respectively. Currently, he is pursuing his Ph.D. degree in Electrical and Computer Engineering at the Georgia Institute of Technology. His research interests include integrated power converters, low-power mixed-signal circuits, and advanced control techniques for power-management ICs.
Visvesh Sathe is an Associate Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He received the B.Tech. degree from the Indian Institute of Technology, Bombay and the M.S. and Ph.D. degrees from the University of Michigan, Ann Arbor. His group, the Processing Systems Lab (PSyLab), works on energy-efficient computing, implantable electronics, and run-time hardware optimization for digital and mixed-signal systems. He has previously held positions at the University of Washington, and in the Low-Power Advanced Development Group at AMD. His work at AMD involved inventing and translating energy-efficient circuit technologies such as resonant clocking and adaptive clocking for supply droop mitigation into production microprocessors.
Visvesh is the recipient of an NSF Career award in 2019 and the Intel outstanding researcher award in 2021. He serves on the technical program committee of the IEEE Custom Integrated Circuits Conference (CICC) and the International Solid-State Circuits Conference (ISSCC). He also serves in the SSCS Webinar committee, and as a distinguished lecturer of the Solid-State Circuits Society.
Contact
Email: sathe__at__gatech__dot__edu
Multi-core server processors, heterogeneous mobile SoCs, and an increasing number of IoT applications can experience significant power and performance benefits from PLL lock-time reduction during wakeup (cold-start) and re-lock. Existing PLLs feature lock-times of approximately 100 REFCLK cycles: for relock. Fast lock-techniques have been proposed but they assume no temperature variation, require prior knowledge of PVT gain or incur significant steady-state performance degradation. In this project, we proposed, and successfully demonstrated a technique that performs runtime computation of accurate phase-frequency PLL equations to robustly achieve phase-lock 8x more rapidly than traditional all-Digital PLL (ADPLL) architectures. To further support Computational Lock, we also developed a novel wide dynamic-range, high resolution and fast resolving TDC architecture. Computational Lock does not impact steady-state PLL operation and can be applied to a broad range of ADPLLs. We demonstrate the proposed technique on a 1-2 GHz ADPLL intended for system clocking applications in 65nm CMOS.
More details can be found in our VLSI Symposium Paper.
Integrated circuits for ultra-low power applications strive to minimize total system energy while satisfying performance requirements. The supply voltage (Vdd) can be set to a Minimum Energy Point (MEP), where leakage and dynamic energy are suitably balanced. However, controlling operating frequency (fclk) while concurrently tracking a MEP sensitive to PVT and switching activity is not possible. Meanwhile, the traditional approach of locking to the minimum required frequency (ftarg), and adjusting Vdd to maintain timing slack precludes the possibility of minimum energy computing. Therefore, there exists a need for a minimum energy computing architecture that meets performance requirements.
Prior work has demonstrated MEP tracking across PVT and switching activity variation. The approach relies on large capacitors for sample-and-hold operation at subthreshold frequencies, and cannot account for the significant regulator losses (often amounting to 10%–50% of total energy) necessary for total system energy minimization. Furthermore, clock generation using a free-running oscillator is a requirement in prior work, precluding any regulation of fclk.
This effort explores a digital architecture for total system energy minimization subject to perfor-mance requirements (see Figure). The design supports two modes of operation — MEP-lock and perf-lock — and seamless, uninterrupted execution during transitions between them. In MEP-lock¬, the design tunes Vdd to first search for and then track the minimum total Energy Per Cycle (tEPC) point inclusive of regulator losses.
More details can be found in our upcoming ISSCC Paper.
Low-Dropout Regulators (LDOs) play an important role in enabling fine-grained supply-voltage domains for energy-efficient SoC design [1]. Digital LDOs are of particular interest due to integration and scalability advantages, but their transient response is slowed down by intrinsic limitations in sam-pled feedback systems. Design margins to ensure stability across worst-case PVT conditions further degrade transient response. Meanwhile, voltage domains continue to shrink in size, thus mandating a faster LDO response to compensate for reduced available decoupling capacitance (decap).
Recently reported non-linear control and event-driven architectures offer fast recovery times. However, non-linear approaches face the challenge of ensuring stable mode transitions under ran-dom load current (IL) conditions. Event-driven LDOs trigger logic to control MOS devices based on threshold crossings made by the regulated voltage (Vout). However, typical digital systems exhibit constant load fluctuation which can result in prohibitive switching losses. To address the impact of worst-case margining, adaptive LDO designs have also been proposed but they largely focus on suppressing Vout ripple and compensating for load current variation.
This work presents computational regulation, a technique for fast and stable transient response across PVT. This concept is demonstrated in a Digital LDO that drives a Cortex-M0 processor with an integrated linear algebra accelerator (Figure above). The key idea is to (1) derive time-domain models that are more accurate than those obtained from the traditional discrete-time transfer function and (2) evaluate the resulting state equations at runtime for rapid regulator response. We also introduce Au-tonomous Gain Tracking (AGT), a low-overhead, low-complexity technique that examines Vout statis-tics for runtime loop gain tuning to enable rapid LDO response across PVT.
In many respects, depending on context and the system in question, computational control can be viewed as a practical take on dead-beat control or as a (significantly) simplified implementation of model-predictive control.
Preliminary results on our research in this area will be presented at ISSCC 2019.