PSyLab

Digital, Mixed-signal and Integrated Power Circuits and Architectures

Research

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Computationally-Controlled LDOs

Computational regulation relies on an accurate time-domain model of the regulator, and evaluates it at runtime to determine the optimal number of headers required for rapid droop response. The system also proposes a new technique to address the urgent problem of loop-gain variation in digital LDOs due to the changes that Vin, Vout and Temperature have on unit-header current. The basic idea is to use low-precision statistical analysis of the output voltage waveform to determine the optimal loop gain

Low-Dropout Regulators (LDOs) play an important role in enabling fine-grained supply-voltage domains for energy-efficient SoC design [1]. Digital LDOs are of particular interest due to integration and scalability advantages, but their transient response is slowed down by intrinsic limitations in sam-pled feedback systems. Design margins to ensure stability across worst-case PVT conditions further degrade transient response. Meanwhile, voltage domains continue to shrink in size, thus mandating a faster LDO response to compensate for reduced available decoupling capacitance (decap).

Recently reported non-linear control and event-driven architectures offer fast recovery times. However, non-linear approaches face the challenge of ensuring stable mode transitions under ran-dom load current (IL) conditions. Event-driven LDOs trigger logic to control MOS devices based on threshold crossings made by the regulated voltage (Vout). However, typical digital systems exhibit constant load fluctuation which can result in prohibitive switching losses. To address the impact of worst-case margining, adaptive LDO designs have also been proposed but they largely focus on suppressing Vout ripple and compensating for load current variation.

This work presents computational regulation, a technique for fast and stable transient response across PVT. This concept is demonstrated in a Digital LDO that drives a Cortex-M0 processor with an integrated linear algebra accelerator (Figure above). The key idea is to (1) derive time-domain models that are more accurate than those obtained from the traditional discrete-time transfer function and (2) evaluate the resulting state equations at runtime for rapid regulator response. We also introduce Au-tonomous Gain Tracking (AGT), a low-overhead, low-complexity technique that examines Vout statis-tics for runtime loop gain tuning to enable rapid LDO response across PVT.

In many respects, depending on context and the system in question, computational control can be viewed as a practical take on dead-beat control or as a (significantly) simplified implementation of model-predictive control.

Preliminary results on our research in this area will be presented at ISSCC 2019.

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Switched-Capacitor UniCAP

The proliferation of Internet-of-Things (IoT) devices has provided an unprecedented demand for ultra-low power systems, where dissipative Process, Voltage and Temperature (PVT) related supply margins, and low cost, low form-factor power management solutions are key considerations. Switched Capacitor (SC) converters are well-suited to such systems and offer efficient integrated DC-DC conversion. However, poor load regulation results in additional droop guard-bands, amplifying the existing problem of PVT-margin related inefficiencies. Another challenge facing low-voltage (near- and sub-threshold) systems is the need to achieve fine-grained voltage scalability with good load regulation. Several integrated voltage regulation (IVR) solutions have been proposed to address supply and PVT-related margins.

This project sees to develop an all-digital Unified Clock and Power (UniCaP) architecture for performance-regulation of near-Vth and sub-Vth digital systems, and demonstrate its effectiveness on an ARM Cortex-M0 processor with an FFT accelerator. UniCaP is based on the observation supply-voltage control in low-voltage digital systems is tasked with ensuring timing-slack. The central idea behind this UniCaP design is to use canary-based oscillators powered by the noisy load domain (Vdd) to guarantee timing compliance, and incorporate voltage-regulation into a Frequency Locked Loop to control Vdd to regulate system operating frequency (fclk) under PVT variation and supply noise. Key features demonstrated by test measurements include (i) a 92% average reduction in supply-droop margin (ii) 98% reduction of temperature related Vdd margins amounting to XmV (YmV) at 0.45V (0.56V) Vdd in the -20C—100C range (iii) continuous SC Vdd-scalability with excellent load and line regulation (iv) a floating split-level supply rail for robust, efficient SC operation independent of Vdd conversion and (v) simplified, on-the-fly DVFS avoiding use of Voltage-frequency tables and enabling uninterrupted processor operation.

Preliminary results on our research in this area were presented at ISSCC 2018.

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Buck Converter UniCAP

Unified Clock and Power (UniCaP) combines the traditionally disparate clock and power sub-systems into a single control structure to enable unprecedented regulation capabilities, and the ability to virtually eliminate droop and temperature related supply-margins

Integrated Voltage Regulation (IVR) using buck converters enables efficient, fine-grained supply-voltage control in modern SoC domains. However, existing IVR implementations face several challenges. As voltage domains continue to shrink, reduced per-domain decoupling capacitance requires rapid IVR transient response, leading to unfavorable efficiency and supply droop margin trade-offs. Additionally, digital domains exhibit a wide load current (Iload) range, requiring capabilities for autonomous transition between Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). All-digital IVR solutions are particularly desirable for ease of integration in SoCs.

Several techniques have been proposed to address these IVR challenges, including adaptive clocking techniques that maintain timing-slack by injecting load-domain supply (Vdd) noise into Phase-locked Loops (PLLs) to modulate the clock period (Tclk). However, benefits observed using these techniques are limited by Vdd-delay sensitivity mismatch between critical paths and the PLL oscillator, and by the undesirable phase tracking mechanism of conventional PLLs. Importantly, existing adaptive clocking techniques are unable to completely restore cycles lost or gained during Vdd transients, a highly desirable feature for inter-domain data communication and real-time applications.

This project has resulted in a unified clock and power (UniCaP) architecture that exploits joint supply-voltage and phase/frequency control to aggressively reduce dissipative Vdd margins arising from supply-noise and temperature variation. In addition, UniCaP enables complete recovery of any cycles gained or lost during supply noise events.

Preliminary results on our research in this area were presented at ISSCC 2018.

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Quasi-Resonant Clocking

Quasi-Resonant Clocking (QRC) exploits run-time control to generate trapezoidal-shaped resonant clocks

Clock power remains a substantial contributor to power dissipation, from ultra-low power to high-performance systems. Recently, resonant clocking has been shown to achieve power reduction in clock distribution networks. However, the limited voltage-frequency (VF) scalability of resonant clocking implementations remains a key drawback. Continued aggressive use of DVFS will require efficient resonant clocking across the increasingly wider operating range of the system. In this paper, we present a test-chip implementing Quasi-Resonant Clocking (QRC), the first-ever voltage-scalable, frequency-independent and DVFS enabled resonant clock architecture. The test-chip achieves a 32%-47% clock power reduction over a 0.7V-1.2V supply-voltage range.

More details can be found in our ISSCC paper.

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On-Chip Power Supply Measurement

An all-digital gated ring-oscillator based power supply monitor relying on deterministic dither for enhanced resolution.

Supply-noise measurement techniques are becoming increasingly critical in modern digital design, driven by the trend toward smaller, lower-voltage domains. All-digital measurement modules capable of meeting bandwidth and resolution requirements would enable spatially fine supply voltage measurements across Systems-on-Chip. Existing implementations either use analog techniques, limiting their applicability, or do not meet the increasingly challenging requirements of supply noise measurement. In this paper we discuss a bandwidth-resolution-reconfigurable all-digital system that relies on a dithering technique to achieve a resolution of 2.05 mV at a bandwidth of 6.94 GHz in an industrial 65 nm CMOS process.